From 9625f4ef05031773a52ebe3ca84db64af68956d6 Mon Sep 17 00:00:00 2001 From: Xudong Hao Date: Mon, 24 Feb 2014 12:11:53 +0100 Subject: [PATCH] x86: expose RDSEED, ADX, and PREFETCHW to dom0 This patch explicitly exposes Intel new features to dom0, including RDSEED and ADX. As for PREFETCHW, it doesn't need explicit exposing. Signed-off-by: Xudong Hao Signed-off-by: Liu Jinsong Reviewed-by: Jan Beulich --- xen/arch/x86/traps.c | 2 ++ xen/include/asm-x86/cpufeature.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 0bd43b9b11..c736dd1298 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -829,6 +829,8 @@ void pv_cpuid(struct cpu_user_regs *regs) cpufeat_mask(X86_FEATURE_BMI2) | cpufeat_mask(X86_FEATURE_ERMS) | cpufeat_mask(X86_FEATURE_RTM) | + cpufeat_mask(X86_FEATURE_RDSEED) | + cpufeat_mask(X86_FEATURE_ADX) | cpufeat_mask(X86_FEATURE_FSGSBASE)); else b = 0; diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 1cfaf948b2..87d5f66c15 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -148,6 +148,8 @@ #define X86_FEATURE_INVPCID (7*32+10) /* Invalidate Process Context ID */ #define X86_FEATURE_RTM (7*32+11) /* Restricted Transactional Memory */ #define X86_FEATURE_NO_FPU_SEL (7*32+13) /* FPU CS/DS stored as zero */ +#define X86_FEATURE_RDSEED (7*32+18) /* RDSEED instruction */ +#define X86_FEATURE_ADX (7*32+19) /* ADCX, ADOX instructions */ #define X86_FEATURE_SMAP (7*32+20) /* Supervisor Mode Access Prevention */ #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability) -- 2.30.2